Image compression device and method

ABSTRACT

An image compression device is disclosed that is capable of quickly compressing image data to a target value by a simple configuration while maintaining quality of a reproduced image as much as possible. The image compression device includes an encoding part, a code reduction part, and a processing part. The encoding part performs a frequency analysis for original image data, encodes the coefficients generated by the frequency analysis first unit by first unit, and generates a series of codes. The code reduction part reduces the amount of the codes of each of the first units. The processing part divides the coefficients or the codes of each of the first units into second units, and increases the amount of codes to be reduced in the code reduction part for each of the second units according to values of the coefficients or the codes of each of the second units.

TECHNICAL FIELD

The present invention relates to an image compression device forencoding image data according to the JPEG 2000 standard or others, and amethod thereof.

BACKGROUND ART

In the recent years, the JPEG 2000 standard has become a well knownmethod especially for compressing and encoding high definition images.When encoding an image according to the JPEG 2000 algorithm, originalimage data are transformed into a number of color components, forexample, into Y, Cb, and Cr color components. Two-dimensional discretewavelet transformation (2D-DWT) is carried out on data of each colorcomponent to perform frequency analysis, and this transformationproduces wavelet coefficients, each of which is represented by, forexample, 16-bit data. The thus obtained wavelet coefficients are dividedinto sub-bands, which are units of processing. For example, in wavelettransformation at level three, there are sub-bands 3LL, 3HL, 3LH, 3HH,2HL, 2LH, 2HH, 1HL, 1LH, and 1HH. In each sub-band, the waveletcoefficients are divided into bit-planes. In each sub-band, the waveletcoefficients contained in the bit-planes are scanned from the mostsignificant bit (MSB) to the least significant bit (LSB) through threetypes of coding passes, and then encoding is performed by arithmeticcoding. The three types of coding passes are referred to as “significantpropagation pass”, “magnitude refinement pass”, and “cleanup pass”.

Compression of the codes are achieved by successively and uniformlytruncating the codes, obtained by scanning through the above threepasses, of a coding pass through all code blocks in each sub-bandsequentially from the bit-planes of the least significant bits. Here,the term “truncating” means to set a target bit to zero, which indicatesinvalid data. The coding method of the JPEG 2000 algorithm is describedin detail in “Overview of the new international standards (JPEG 2000)for coding of still images”, The Journal of the Institute of ImageInformation and Television Engineers, pp 164-171, Vol. 54, No. 2, 2000.

In the coding process of JPEG 2000, as described above, image data canbe easily compressed to a preset target value by successively truncatingthe codes of a coding pass corresponding to the bit-planes of the leastsignificant bits in each sub-band. However, depending on the method oftruncating, sometimes the quality of the reproduced image, which is theimage obtained by decoding the compressed codes, may be greatlydegraded.

DISCLOSURE OF THE INVENTION

It is a general object of the present invention to solve one or more ofthe problems of the related art.

A specific object of the present invention is to provide an imagecompression device and image compression method capable of quicklycompressing image data to a target value by a simple configuration whilemaintaining quality of a reproduced image as much as possible.

To attain the above objects, according to a first aspect of the presentinvention, there is provided an image compression device comprising anencoding part that performs a frequency analysis on image data, encodesa plurality of coefficients generated by the frequency analysis firstunit by first unit, and generates a plurality of codes; a code reductionpart that reduces the amount of the codes of each of the first units;and a processing part that further divides the coefficients or the codesof each of the first units into a plurality of second units, andincreases the amount of code reduction in the code reduction part foreach of the second units according to values of the coefficients of eachof the second units or according to values of the codes of each of thesecond units.

In an embodiment, the code reduction part comprises a truncation tableincluding a plurality of truncation data sets to each of which a datanumber is assigned, said truncation data sets determining the amount ofcodes to be truncated from the least significant bit of the codescorresponding to one of the coefficients in each of the first units,said truncation data sets being arranged so that along with an increaseof the data number, the amount of the codes to be truncated increases ordecreases gradually, and the image quality degrades or improvesgradually; and a rate controller that determines one of the data numberscorresponding to one of the truncation data, said one of the truncationdata sets resulting in a change of the amount of the codes of each ofthe first units after code truncation in accordance with the one of thetruncation data sets to be close to a target value.

In an embodiment, the image compression device performs coding incompliance with the JPEG 2000 standards. In the image compressiondevice, the encoding part performs a two-dimensional discrete wavelettransformation on the image data and generates a plurality of waveletcoefficients, divides the wavelet coefficients into a plurality ofsub-bands, performs arithmetic coding for the wavelet coefficients ineach sub-band and generates a plurality of codes; the code reductionpart reduces the amount of the codes by truncating a portion of thecodes corresponding to one of the wavelet coefficients from the leastsignificant bit of the codes in each of the sub-bands; and theprocessing part divides each of the sub-bands into a plurality of codeblocks, and increases the amount of the codes to be truncated for eachcode block in the code reduction part according to values of the waveletcoefficients in each of the code blocks or according to values of dataobtained by processing the wavelet coefficients of each of the codeblocks.

In an embodiment, the processing part comprises an average valuecalculation circuit that calculates an average value of the waveletcoefficients of a plurality of effective pixels in each of the codeblocks, or an average value of the data obtained by processing thewavelet coefficients of the effective pixels in each of the code blocks;and a masking coefficient calculation circuit that determines theincrease of the amount of the codes to be truncated in each of the codeblocks performed in the code reduction part according to the averagevalue obtained in the average value calculation circuit.

In an embodiment, the average value calculation circuit quantizes thewavelet coefficients of the effective pixels in each of the code blocks,and calculates the average value of the data obtained by quantizing thewavelet coefficients.

In an embodiment, the average value calculation circuit encodes thewavelet coefficients of the effective pixels in each of the code blocksby arithmetic coding, and calculates the average value of data obtainedby encoding the wavelet coefficients.

According to a second aspect of the present invention, there is providedan image compression method comprising the steps of performing afrequency analysis on image data, encoding a plurality of coefficientsobtained by the frequency analysis first unit by first unit, andgenerating a plurality of codes; reducing the amount of the codes ofeach of the first units; and further dividing the coefficients or thecodes of each of the first units into a plurality of second units, andincreasing the amount of reduction of the codes for each of the secondunits according to values of the coefficients of each of the secondunits or according to values of the codes of each of the second units.

According to a third aspect of the present invention, there is provideda program for compressing image data, comprising instructions forcausing a computer to execute: a first step of performing a frequencyanalysis on the image data, encoding a plurality of coefficientsobtained by the frequency analysis first unit by first unit, andgenerating a plurality of codes; a second step of reducing the amount ofthe codes of each of the first units; and a third step of furtherdividing the coefficients or the codes of each of the first units into aplurality of second units, and increasing the amount of code reductionfor each of the second units according to values of the coefficients ofeach of the second units or according to values of the codes of each ofthe second units.

According to a fourth aspect of the present invention, there is provideda storage medium that stores a program for compressing image data andcomprising instructions for causing a computer to execute: a first stepof performing a frequency analysis on the image data, encoding aplurality of coefficients obtained by the frequency analysis first unitby first unit, and generating a plurality of codes; a second step ofreducing the amount of the codes of each of the first units; and a thirdstep of further dividing the coefficients or the codes of each of thefirst units into a plurality of second units, and increasing the amountof code reduction for each of the second units according to values ofthe coefficients of each of the second units or according to values ofthe codes of each of the second units.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, and advantages of the presentinvention will become more apparent from the following detaileddescription of preferred embodiments given with reference to theaccompanying drawings, in which:

FIGS. 1A through 1C are diagrams for briefly explaining code truncationperformed in an image compression device 100 according to a firstembodiment of the present invention;

FIG. 2 shows a table for explaining a method of code truncationaccording to the present embodiment;

FIG. 3 is a block diagram showing a configuration of the imagecompression device 100 according to the first embodiment of the presentinvention;

FIG. 4 is diagram showing a memory map of codes loaded in DRAM 50 of theimage compression device 100 according to the first embodiment of thepresent invention;

FIG. 5 is a diagram explaining the average value of the waveletcoefficients of the effective pixels in a code block according to thefirst embodiment of the present invention;

FIG. 6 is a circuit diagram showing a configuration of the maskingcoefficient calculation circuit 27 of the image compression device 100according to the first embodiment of the present invention;

FIG. 7 is a diagram showing a memory map of the memory A of the imagecompression device 100 according to the first embodiment of the presentinvention;

FIG. 8 is a diagram showing a memory map of the memory C of the imagecompression device 100 according to the first embodiment of the presentinvention;

FIG. 9 is a flowchart showing the operation of the data processingcircuit 29 of the image compression device 100 according to the firstembodiment of the present invention;

FIG. 10 is a block diagram showing a configuration of the rate controlcircuit 32 of the image compression device 100 according to the firstembodiment of the present invention;

FIG. 11 is flowchart showing the operation of the data number switchingcircuit 90 of the image compression device 100 according to the firstembodiment of the present invention;

FIG. 12 is a flowchart showing the operation of the packet informationgeneration circuit 34 of the image compression device 100 according tothe first embodiment of the present invention;

FIG. 13 is a block diagram showing a configuration of an imagecompression device 200 according to a second embodiment of the presentinvention;

FIG. 14 is a flowchart showing the operation of the data processingcircuit 210 of the image compression device 200 according to the secondembodiment of the present invention;

FIG. 15 is a diagram showing a memory map of the memory C of the imagecompression device 200 according to the second embodiment of the presentinvention.

FIG. 16 is a block diagram showing a configuration of the rate controlcircuit 220 of the image compression device 200 according to the secondembodiment of the present invention;

FIG. 17 is a block diagram showing a configuration of an imagecompression device 300 according to a third embodiment of the presentinvention;

FIG. 18 is a flowchart showing the operation of the data processingcircuit 310 of the image compression device 300 according to the thirdembodiment of the present invention; and

FIG. 19 is a block diagram showing a configuration of the rate controlcircuit 320 of the image compression device 300 according to the thirdembodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Below, preferred embodiments of the present invention are explained withreference to the accompanying drawings.

First Embodiment

1. General Description of Code Truncation

FIGS. 1A through 1C are diagrams for briefly explaining code truncationperformed in an image compression device 100 according to a firstembodiment of the present invention.

Below, for purpose of illustration, an explanation is made of coding ofimage data consisting of 128×128 pixels, as shown in FIG. 1A. First, theimage data in FIG. 1A are transformed into a number of color components,for example, into Y, Cb, and Cr color components. Here, since thesubsequent processing for different color components is the same, below,the description is made with the Y component as an example.

On the data of the Y color component, two-dimensional discrete wavelettransformation (2D-DWT) is carried out to perform frequency analysis,and this transformation generates 16-bit wavelet coefficients. Toperform the subsequent processing with sub-bands as units, the waveletcoefficients are divided into groups respectively related to sub-bands3LL, 3HL, 3LH, 3HH, 2HL, 2LH, 2HH, 1HL, 1LH, and 1HH, as shown in FIG.1B. These wavelet coefficients are also divided into 16 bit-planes. Ineach sub-band, the 16-bit wavelet coefficients contained in the 16bit-planes are scanned from the most significant bit to the leastsignificant bit through three types of coding passes, and then encodingis performed by arithmetic coding. The three types of coding passes arethe significant propagation pass, the magnitude refinement pass, and thecleanup pass. As a result, in each sub-band, codes of a total of 46coding passes are generated. This is shown in FIG. 1C.

The image compression device 100 according to the first embodimenttruncates the codes of a coding pass in each sub-band sequentially fromthe bit-plane of the least significant bit to the bit-plane of the mostsignificant bit. There are two methods for such code truncation.

The first method is explained below with reference to FIG. 2.

In the first method of code truncation, first, a truncation table isprepared which contains data sets managed in terms of colors andsub-bands. Each data set in the truncation table determines the numberof coding passes codes in which are to be truncated each time from thebit-plane of the least significant bit in each sub-band (3LL, 3HL, 3LH,3HH, 2HL, 2LH, 2HH, 1HL, 1LH, and 1HH). Below, the data contained in thetruncation table are referred to as “truncation data”, and each data setcontained in the truncation table is referred to as “truncation dataset”.

FIG. 2 shows an example of the truncation table according to the presentembodiment. As shown in FIG. 2, the truncation table contains more than1500 truncation data sets.

For example, a truncation data set 1, 1 1 1, 1 1 1, 2 2 2 is defined.This truncation data set, as illustrated by the dashed lines in FIG. 1C,specifies the number of coding passes, codes in which are to betruncated sequentially from the bit-plane of the least significant bitto the bit-plane of the most significant bit, each of the coding passesbeing through all of the code blocks in each sub-band, which is the unitof processing in arithmetic coding.

Specifically, the truncation data set 1, 1 1 1, 1 1 1, 2 2 2 specifiesthat codes of one coding pass are truncated from each of the sub-bandsat level three: 3LL, 3HL, 3LH, and 3HH, codes of one coding pass aretruncated from each of the sub-bands at level two: 2HL, 2LH, and 2HH,and codes of two coding passes are truncated from each of the sub-bandsat level one: 1HL, 1LH, and 1HH.

In the truncation table of FIG. 2, the truncation data sets are arrangedso that as the data number of the truncation data set increases, thedata in the truncation data set increase accordingly, indicating thatmore codes are to be truncated, and as a result, leading to lowerquality of the reproduced image.

Certainly, the truncation data sets may also be arranged so that as thedata number increases, data in the corresponding truncation data setdecrease accordingly, indicating that fewer codes are to be truncated,and as a result, leading to higher quality of the reproduced image. Sucha truncation table and the corresponding processing are discussed belowwhere necessary.

The truncation data are created based on experiments using sampleimages, or based on statistics of experimental results using varioussample images. Moreover, a number of truncation tables may be preparedbeforehand, and when capturing a moving image, the truncation table inuse may be switched depending on the amount of movement of the objectbetween successive frames.

In the image compression device 100 of the present embodiment, the codesof each coding pass in each sub-band, which are obtained by thearithmetic coding performed on data contained in the 16 bit-planes ineach sub-band, are stored in a memory (memory A and memory B shown inFIG. 3), the amount of the codes to be truncated is calculated from theamount of codes stored in the memory, and the deficiency of the amountof codes to be truncated relative to a target value is obtained. If thecalculated amount of codes to be truncated is less than the targetvalue, a truncation data set corresponding to a larger data number maybe selected, giving a greater amount of codes to be truncated. If thecalculated amount of codes to be truncated is greater than the targetvalue, a truncation data set corresponding to a larger data number maybe selected, giving a lesser amount of codes to be truncated.

When compressing codes using the first method of code truncation, bypreparing truncation data sets arranged in such an order that the amountof codes to be truncated increases as the data number increases, thatis, the image quality decreases as the data number increases, it is notnecessary to perform the process of decoding the codes after codetruncation according to the JPEG 2000 algorithm and determine distortionrelative to the image prior to the code truncation, to determine a wayof code truncation resulting in the least distortion.

As described above, in the first method, codes of a specified number ofcoding passes, given by a truncation data set in the truncation table ineach sub-band, are equally truncated.

Meanwhile, in the second method of code truncation, in comparison to thefirst method, each sub-band is further divided into a number of codeblocks, which are used as the second unit for processing. In each codeblock, the number of coding passes to be truncated is increased by anumber determined according to the magnitude of the waveletcoefficients, or magnitude of data obtained by processing the waveletcoefficients.

Generally, in the same sub-band, if the amount of codes to be truncatedchanges code block by code block, noticeable distortion occurs in thereproduced image at the boundaries between code blocks. For this reason,it is common to truncate codes sub-band by sub-band. In this embodiment,to solve the above problem, the second method is devised to be based ona characteristic of the human visual sense, that is, within a sub-band,particularly, in a region having more image components (an imagecomponent means an average value of wavelet coefficients of effectivepixels, or an average value of data obtained by processing the waveletcoefficients of the effective pixels), even when a large amount of codesare truncated, a person does not perceive noticeable image distortion,and the person feels just moderate degradation of image quality.Therefore, by exploiting such a characteristic, it is possible toincrease the rate of compression while maintaining the quality of thereproduced image as high as possible.

In detail, in each sub-band, the number of coding passes to be furthertruncated in each code block is determined according to an average valueof the wavelet coefficients or an average value of data obtained byprocessing the wavelet coefficients of the effective pixels in the codeblock. For example, the number of coding passes to be further truncatedin each code block is in the range from zero to two.

In FIG. 1C, each sub-band is divided into code blocks, which are markedoff by dashed lines. The number of coding passes to be further truncatedin each code block is presented in each code block, and the codingpasses to be truncated are cross-hatched.

In this way, by adjusting the number of coding passes to be truncated ineach code block, it is possible to perform code truncation moreeffectively while preventing degradation of quality of the reproducedimage.

2. Configuration of Image Compression Device

FIG. 3 is a block diagram showing a configuration of an imagecompression device 100 according to a first embodiment of the presentinvention.

The image compression device 100 includes a wavelet transformation unit10, an arithmetic coding unit 20, a packet header generation unit 30, amemory controller 40, and a DRAM 50.

The memory controller 40 is a so-called arbiter circuit, whicharbitrates access to the DRAM 50 of DMA 13 in the wavelet transformationunit 10; DMA 21 and DMA 25 in the arithmetic coding unit 20; and DMAs31, 33, 35 and 37 in the packet header generation unit 30.

The DRAM 50 holds the aforementioned truncation data shown in thetruncation table presented in FIG. 2, and the codes of all sub-bands ofan image frame that is being processed.

Next, configurations and operations of the wavelet transformation unit10, the arithmetic coding unit 20, and the packet header generation unit30 are explained below with reference to FIG. 4 through FIG. 12.

2.1 Wavelet Transformation Unit 10

The wavelet transformation unit 10 transforms input image data into16-bit wavelet coefficients.

The wavelet transformation unit 10 includes a color transformationcircuit 11, a wavelet transformation circuit 12, and the DMA 13.

The color transformation circuit 11 transforms the original image datainto color components Y, Cb, and Cr, and output the data of the colorcomponents Y, Cb, and Cr.

The wavelet transformation circuit 12 carries out the two-dimensionaldiscrete wavelet transformation (2D-DWT) on the data of each colorcomponent, and produces the 16-bit wavelet coefficients.

The DMA 13 transfers the thus obtained 16-bit wavelet coefficients to aspecified address of the DRAM 50.

Here, well-known circuits are used for the color transformation circuit11 and the wavelet transformation circuit 12.

2.2 Arithmetic Coding Unit 20

The arithmetic coding unit 20 includes DMA 21, a quantization unit 22, abit-plane division circuit 23, an arithmetic coding circuit 24, DMA 25,an average calculation circuit 26, a masking coefficient calculationcircuit 27, a code amount calculation circuit 28, and a data processingcircuit 29.

The arithmetic coding unit 20 carries out arithmetic coding for the16-bit wavelet coefficients stored in the DRAM 50, and loads thegenerated codes of each coding pass in each sub-band in the DRAM 50.Further, the arithmetic coding unit 20 determines the number of thecoding passes in each code block in each sub-band, and loads thedetermined number of the coding passes in a memory A and a memory B.Below, “the number of the coding passes in each code block” is referredto as “number of masks” where necessary.

From the determined number of masks and the amount of codes of eachcoding pass in each code block, and based on the truncation data set,the arithmetic coding unit 20 determines the amount of code reductionwhen truncating one coding pass each time in each sub-band, and loadsthe obtained amount of the code reduction in a memory C and memory D.The obtained amount of the code reduction corresponds to the amount ofcodes that is to be further truncated according to the number of masksin each code block.

The DMA 21 reads out the 16-bit wavelet coefficients in each sub-bandstored in the specified address of the DRAM 50.

The quantization unit 22 quantizes the obtained 16-bit waveletcoefficients by Entropy Quantization, and outputs the quantized waveletcoefficients to the bit-plane division circuit 23.

The bit-plane division circuit 23 divides the quantized waveletcoefficients into bit-planes.

The arithmetic coding circuit 24 scans the wavelet coefficientscontained in the bit-planes in each sub-band from the most significantbit to the least significant bit in three types of coding passes, andthen performs arithmetic coding. The three types of coding passes arethe significant propagation pass, the magnitude refinement pass, and thecleanup pass, respectively. Codes output from the arithmetic codingcircuit 24 contain codes of 46 coding passes (15×3+1=46). The arithmeticcoding circuit 24 loads the codes in the DRAM 50 through the DMA 25.

Here, well-known circuits are used for the quantization unit 22, thebit-plane division circuit 23, and the arithmetic coding circuit 24.

FIG. 4 is diagram showing a memory map of the codes stored in DRAM 50.

The codes are loaded in the DRAM 50 in order of 3LL, 3HL, 3LH, 3HH, 2HL,2LH, 2HH, 1HL, 1LH, and 1HH. For example, in the 2HH sub-band, codes of46 coding passes are written in order of assigned code block numbers(CB), for example, 1, 2, . . . , 10, . . . , CB_(2HH-MAX). Here,CB_(2HH-MAX) represents a maximum number assigned to code blocks in the2HH sub-band.

Referring to FIG. 3 again, the wavelet coefficients read out from theDRAM 50 through the DMA 21 are also output to the average calculationcircuit 26. The average calculation circuit 26 calculates the averagevalue of the wavelet coefficients of the effective pixels in each codeblock and then outputs the obtained results. Here, the effective pixelindicates a pixel having an effective wavelet coefficient in the codeblock formed by a certain pixel matrix.

FIG. 5 is a diagram explaining the average value of the waveletcoefficients of the effective pixels in a code block.

As shown in FIG. 5, when the 1LH sub-band including 64 (vertical)×62(horizontal) pixels is divided into code blocks each having 16×16pixels, in the code blocks positioned along the right side in FIG. 5,the 16 (vertical)×2 (horizontal) pixels on the right side of these codeblocks, each of which is marked by a cross (“x”), do not have effectivewavelet coefficients. Therefore, for these code blocks along the rightside, the average value of the wavelet coefficients is calculated byusing the pixels not marked with crosses. Here, a well known circuit isused for the average calculation circuit 26.

The data input to the average calculation circuit 26 includes not onlythe wavelet coefficients of each code block, but also data obtained byprocessing the wavelet coefficients of each code block, for example, thedata obtained by quantizing the wavelet coefficients of each code blockin the quantization unit 22, or codes of each code block obtained bycoding the wavelet coefficients of each code block in the arithmeticcoding circuit 24.

Referring to FIG. 3 again, the masking coefficient calculation circuit27 determines the number of masks (that is, number of coding passes tobe truncated) based on the average value of the wavelet coefficients ofthe effective pixels in each code block output sequentially from theaverage calculation circuit 26. The number of masks, also referred to as“masking coefficient”, is equal to 0, or 1, or 2, indicating the numberof coding passes to be further truncated in each code block. The maskingcoefficient calculation circuit 27 outputs the number of masks to thememory A and memory B.

FIG. 6 is a circuit diagram showing a configuration of the maskingcoefficient calculation circuit 27.

As shown in FIG. 6, the masking coefficient calculation circuit 27includes three comparators 27 a, 27 b, and 27 c, and a selector 27 d.

The average value of the wavelet coefficients of the effective pixels ineach code block (denoted as AVG) is input to one input terminal of eachof the comparators 27 a, 27 b, and 27 c, and three threshold values(TH1, TH2, and TH3) are input to the other input terminals of thecomparators 27 a, 27 b, and 27 c, respectively. Here, it is assumed thatthe three thresholds TH1, TH2, and TH3 satisfy the relation ofTH1<TH2<TH3.

When the data input to the comparator 27 a is greater than the thresholdTH1, the comparator 27 a outputs a high level signal; when the datainput to the comparator 27 a is less than the threshold TH1, thecomparator 27 a outputs a low level signal. Similarly, when the datainput to the comparator 27 b is greater than the threshold TH2, thecomparator 27 b outputs a high level signal; when the data input to thecomparator 27 b is less than the threshold TH2, the comparator 27 boutputs a low level signal. When the data input to the comparator 27 cis greater than the threshold TH3, the comparator 27 c outputs a highlevel signal; when the data input to the comparator 27 c is less thanthe threshold TH3, the comparator 27 c outputs a low level signal.

The selector 27 d outputs the value of the number of masks.Specifically, when all of the comparator 27 a, the comparator 27 b, andthe comparator 27 c output low level signals, the selector 27 d outputsa signal indicating the number of masks is zero; when the comparator 27a outputs a high level signal, and the comparator 27 b and thecomparator 27 c output low level signals, the selector 27 d outputs asignal indicating the number of masks is one; when the comparator 27 aand the comparator 27 b output high level signals, and the comparator 27c outputs a low level signal, the selector 27 d outputs a signalindicating the number of masks is two; when all of the comparator 27 a,the comparator 27 b, and the comparator 27 c output high level signals,the selector 27 d outputs a signal indicating the number of masks isthree.

Referring to FIG. 3 again, the memory A and the memory B arealternatively switched to an enabling state frame by frame to load thenumber of masks for each code block in each sub-band, which is outputfrom the masking coefficient calculation circuit 27.

FIG. 7 is a diagram showing a memory map of the memory A. The memory Bhas the same memory map as the memory A.

As shown in FIG. 7, in the memory A, there are loaded the numbers ofmasks of the code blocks in each of sub-bands 3LL, 3HL, 3LH, 3HH, 2HL,2LH, 2HH, 1HL, 1LH, and 1HH. For example, in the 2HH sub-band, numbersof masks for code blocks from CB=1 through CB=CB_(2HH-MAX) are stored.Specifically, for the code block having a code block number of 1, thenumbers of masks is zero, for the code block having a code block numberof 2, the numbers of masks is one, for the code block having a codeblock number of 10, the numbers of masks is three, for the code blockhaving a code block number of CB_(2HH-MAX-1), the numbers of masks istwo, and for the code block having a code block number of CB_(2HH-MAX),the numbers of masks is zero.

Here, as already mentioned above, CB_(2HH-MAX) represents the maximumnumber assigned to code blocks in the 2HH sub-band. For example,CB_(2HH-MAX) equals 16 in FIG. 7.

Referring to FIG. 3 again, the arithmetic coding circuit 24 also outputscodes to the code amount calculation circuit 28.

The code amount calculation circuit 28 counts the codes of each of thecoding passes corresponding to the bit-planes in each code block, andoutputs the count to the data processing circuit 29.

The numbers of masks of code blocks (numbers of coding passes of codeblocks) loaded in the memory A and the memory B are also output to thedata processing circuit 29. When truncating the codes of the codingpasses in each sub-band from the bit-plane of the least significant bitcoding pass by coding pass, the data processing circuit 29 furthercalculates the amount of the codes truncated according to the number ofmasks, and loads the obtained amount of codes to be truncated in amemory C and a memory D.

FIG. 8 is a diagram showing a memory map of the memory C. The memory Dhas the same memory map with the memory C.

As shown in FIG. 8, in the memory C, at an address ADD3LL, there areloaded the data indicating the amount of the codes to be truncated whentruncating the codes of the 46 coding passes in the 3LL sub-band fromthe bit-plane of the least significant bit.

Similarly, at addresses ADD3HL, ADD3HL, ADD3HH, ADD2HL, ADD2LH, ADD2HH,ADD1HL, ADD1LH, and ADD1HH, there are respectively loaded the dataindicating the amounts of codes to be truncated from the respectivesub-bands.

Further, FIG. 8 shows specific data stored at address from ADD1LH toADD1HH, that is, the amount of codes of coding passes to be truncatedfrom the bit-plane of the least significant bit. Here, the amount ofcodes to be truncated is denoted as Sn, where n takes values from 0 to46, and the amount of codes to be truncated is defined to have aspecified bit length, for example, 20 bits.

If the offset address ADD_(OFF) is determined, which is related to a20-bit long storage region, data indicating the amount of codes to betruncated (Sn), when the code pass No. 0 through the code pass No. 46are truncated one by one sequentially, may be stored at an address equalto the sum of an address ADD1LH and the offset address ADD_(OFF)multiplied by the number of the coding passes to be truncated, that is,the amounts of codes to be truncated (Sn) are respectively stored ataddresses ADD1LH, ADD1LH+ADD_(OFF), ADD1LH+2×ADD_(OFF),ADD1LH+3×ADD_(OFF), . . . , and ADD1LH+46×ADD_(OFF).

FIG. 9 is a flowchart showing the operation of the data processingcircuit 29. Here, if the flowchart shown in FIG. 9 is input to a logicsynthesis tool made by the company Synopsys, USA, a specific circuit canbe automatically designed.

First, sub-bands are defined corresponding to values of a sub-banddetermining parameter SB. Specifically, SB=1 corresponds to a sub-band3LL, SB=2 corresponds to the sub-band 3HL, SB=3 corresponds to thesub-band 3LH, SB=4 corresponds to the sub-band 3HH, SB=5 corresponds tothe sub-band 2HL, SB=6 corresponds to the sub-band 2LH, SB=7 correspondsto the sub-band 2HH, SB=8 corresponds to the sub-band 1HL, SB=9corresponds to the sub-band 1LH, and SB=10 corresponds to the sub-band1HH.

As shown in FIG. 9, in step S1, the data processing circuit 29 sets theparameter SB equal to one.

In step S2, the data processing circuit 29 sets a parameter BP equal tozero, and a variable S_(BP) equal to zero. The parameter BP determinesthe number of the coding passes, codes in which are to be truncated. Thevariable S_(BP) indicates reduction of the amount of codes when a numberof BP coding passes are truncated one by one from the bit-plane of theleast significant bit. The reduction of the amount of codes is referredto as “change of the amount of codes”.

In step S3, the data processing circuit 29 sets a parameter CB equal toone. The parameter CB determines a code block of the sub-band specifiedby the parameter SB.

In step S4, the data processing circuit 29 sets a parameter Q to a valueequaling the sum of the parameter BP and the number of coding masksM(CB) to be truncated in the code block specified by the parameter CB.That is, the parameter Q indicates a number of the coding passes to beactually truncated in the code block.

In step S5, the data processing circuit 29 calculates a total amount ofcodes (represented by S_(BP)(CB)) of a number of Q coding passes fromthe bit-plane of the least significant bit of the code block specifiedby the parameter CB.

In step S6, if the parameter BP is zero, that is, only codes of a numberof coding passes specified by the number of masks M(CB) are to betruncated, the data processing circuit 29 goes to step S8, where thevalue of the parameter S_(BP) is incremented by the value of thevariable S_(BP)(CB).

If the parameter BP is greater than or equal to one, the data processingcircuit 29 goes to step S7.

In step S7, the data processing circuit 29 assigns the differencebetween the present value of the variable S_(BP)(CB) and the last valueof S_(BP)(CB), that is, S_(BP-1)(CB), to the variable S_(BP)(CB).

In step S8, the data processing circuit 29 increments the value of theparameter S_(BP) by the value of the variable S_(BP)(CB).

In step S9, the data processing circuit 29 increments the parameter CBby one.

In step S10, the data processing circuit 29 determines whether theparameter CB is greater than the maximum number CB_(SB-MAX) assigned tothe code blocks of the sub-band specified by the parameter SB.

If the parameter CB is not greater than the maximum number CB_(SB-MAX),the data processing circuit 29 goes back to step S4. If the parameter CBis greater than the maximum number CB_(SB-MAX), the data processingcircuit 29 goes to step S11.

In step S11, the data processing circuit 29 loads the value of theparameter S_(BP) at an address equaling the sum of an offset addressADD_(OFF)×BP and an address ADD″SB″ in the memory selected from thememory A and the memory B, which are alternatively switched to theenabling state frame by frame.

For example, when the parameter SB is one, as shown in FIG. 8, theaddress ADD″SB″ represents the address ADD3LL.

In step S12, the data processing circuit 29 increments the parameter BPby one.

In step S13, the data processing circuit 29 determines whether theparameter BP is greater than 46. If the parameter BP is not greater than46, the data processing circuit 29 goes back to step S3.

If the parameter BP is greater than 46, that is, all of the 46 codingpasses of the sub-band specified by the parameter BP have beenprocessed, the data processing circuit 29 goes to step S14 to processthe next sub-band.

In step S14, in order to process the next sub-band, the data processingcircuit 29 increments the parameter SB by one.

In step S15, the data processing circuit 29 determines whether theparameter SB is greater than 10, which is the maximum of the parameterSB as defined above.

If the value of the parameter SB is not greater than 10, the dataprocessing circuit 29 returns to step S2.

If the value of the parameter SB is greater than 10, it means that allof the sub-bands have been processed, and the data processing circuit 29stops the routine.

The operations shown by the flowchart in FIG. 9 can be performed bysoftware executed in a not-illustrated central processing unit.

2.3 Packet Header Generation Unit 30

As shown in FIG. 3, the packet header generation unit 30 includes a ratecontrol circuit 32, a packet information generation circuit 34, a packetheader generation circuit 36, a code formation circuit 38, and DMAs 31,33, 35, 37.

The packet header generation unit 30 determines the data numbers of thetruncation data sets appropriate for truncating a desired amount ofcodes. The packet header generation unit 30 determines the data numbersof the truncation data sets based on the amount of codes to be truncatedobtained by the arithmetic coding unit 20, including both the amount ofcodes of coding passes in each sub-band truncated one by one from thebit-plane of the least significant bit, and the amount of codes to betruncated related to the number of masks of each code block. The packetheader generation unit 30 further generates a packet header of codesobtained based on truncation data set specified by the determined datanumber, and generates a bit stream and outputs the bit stream.

The rate control circuit 32 reads out a truncation data setcorresponding to a data number 128, which is defined in the truncationtable in FIG. 2, from the DRAM 50 through the DMA 31. According to thetruncation data set read out from the DRAM 50, the rate control circuit32 calculates the total amount of codes to be truncated determined foreach code block in each sub-band. Then the rate control circuit 32compares the calculated total amount of codes to be truncated with atarget value.

If the calculated total amount of codes to be truncated is less than thetarget value, the rate control circuit 32 reads out the truncation dataset corresponding to a data number greater than the previous one, andaccording to the truncation data set, the rate control circuit 32calculates again the total amount of codes to be truncated in eachsub-band.

If the calculated amount of codes to be truncated is greater than thetarget value, the rate control circuit 32 reads out a truncation dataset corresponding to a data number less than the previous one, andaccording to the truncation data set, the rate control circuit 32calculates again the total amount of codes to be truncated in eachsub-band.

In this way, the rate control circuit 32 determines a truncation dataset that results in a calculated total amount of codes to be truncatedapproximately the same as the target value. The rate control circuit 32outputs the determined truncation data set to the packet informationgeneration circuit 34.

FIG. 10 is a block diagram showing a configuration of the rate controlcircuit 32.

As shown in FIG. 10, the rate control circuit 32 includes an addressgeneration circuit 60, a code amount calculation circuit 80, and a datanumber switching circuit 90.

The address generation circuit 60 and the code amount calculationcircuit 80 read out a truncation data set corresponding to a specifieddata number from the truncation table in FIG. 2, and according to theobtained truncation data set, calculate change of the amount of codeswhen truncating codes of coding passes in each sub-band coding pass bycoding pass from the bit-plane of the least significant bit. That is,the address generation circuit 60 and the code amount calculationcircuit 80 act as a calculating unit for calculating the change of theamount of codes.

Based on the truncation data set input through the DMA 31, the addressgeneration circuit 60 generates an address signal for reading out dataindicating the amount of codes of a bit-plane to be added or subtracted,and outputs the address signal to the memory C or memory D. The dataindicating the amount of codes to be truncated loaded at the specifiedaddress in either the memory C or the memory D, which is in an enabledstate and holds data of the image frame being processed, are output tothe code amount calculation circuit 80.

The code amount calculation circuit 80 sums the amount of codes to betruncated in each sub-band sent from the memory C or the memory D, andcompares the total amount of codes to be truncated with the targetvalue. The code amount calculation circuit 80 generates a signalindicating the comparison result and outputs the signal to the datanumber switching circuit 90.

Based on the comparison result output from the code amount calculationcircuit 80, the data number switching circuit 90, through the DMA 33,makes a request to the DRAM 50 for a truncation data set having adifferent data number.

When a truncation data set is determined to gives a total amount ofcodes to be truncated roughly equal to the target value, the data numberswitching circuit 90 outputs a signal indicating the data number of thetruncation data set to the packet header generation circuit 36.

Below, detailed explanations are made of configurations and operationsof the address generation circuit 60, the code amount calculationcircuit 80, and the data number switching circuit 90.

The address generation circuit 60 includes a shift register 61, acomparator 62, a selector 63, a sub-band selection circuit 64, adown-counter 65, an AND gate 66, a calculation unit 67, a register 68,an accumulator 69, a selector 70, a selector 71, a multiplier 72, and anaccumulator 73.

The truncation data set is input to the shift register 61 of the addressgeneration circuit 60 through the DMA 31.

The shift register 61 stores the present truncation data set and thelast truncation data set. The comparator 62 subtracts the lasttruncation data set from the present truncation data set in eachsub-band (that is, sub-bands 3LL, 3HL, 3LH, 3HH, 2HL, 2LH, 2HH, 1HL,1LH, and 1HH), and outputs the obtained result to the selector 63. Thelast truncation data set in each sub-band is output to the selector 71.

The sub-band selection circuit 64 updates a sub-band selection signal soas to select a next sub-band in response to a request signal input tothe sub-band selection circuit 64 for updating the sub-band selectionsignal. Then the sub-band selection circuit 64 outputs the updatedsub-band selection signal.

In response to the selection signal input from the sub-band selectioncircuit 64, the selector 63 sequentially outputs data indicating thecomparison results related to sub-bands 3LL, 3HL, 3LH, 3HH, 2HL, 2LH,2HH, 1HL, 1LH, and 1HH to the down-counter 65. As for the dataindicating the comparison results, for example, when the 1HL sub-band isselected according to the selection signal, if the last truncation dataset of the 1HL sub-band is one, and the present truncation data set isthree, then the difference of the present truncation data set and thelast truncation data set (+2) is the data indicating the comparisonresult. The selector 63 outputs the comparison result to the downcounter 65.

The down counter 65 sets the data indicating the comparison resultoutput from the selector 63 as a value to be counted down, and starts tocount down. The counting-down value is input to one input terminal ofthe AND gate 66. An output signal from the register 68 is input to theother input terminal of the AND gate 66. That is, when the counter 65 iscounting down, the AND gate 66 outputs the value of the register 68directly to one input terminal of the calculation unit 67. When thecounter 65 completes counting, the AND gate 66 outputs a low levelsignal. The low level signal is output to the sub-band selection circuit64 as the selection signal updating request signal.

The signal from the selector 63 is input to the addition-subtractioncontrol terminal of the calculation unit 67. That is, when anaddition-subtraction control signal indicating positive is input, thecalculation unit 67 accumulates offset address ADD_(OFF) insynchronization with the counting down timing of the down counter 65,and outputs the result to one input terminal of the accumulator 69. Tothe contrary, when an addition-subtraction control signal indicatingnegative is input, the calculation unit 67 subtracts the offset addressADD_(OFF) from the value stored in the register 68 in synchronizationwith the counting down timing of the down counter 65.

The selector 70 outputs the corresponding address ADD (ADD3LL throughADD1HH) to the other input terminal of the accumulator 69 in response tothe selection signal output from the sub-band selection circuit 64. Theaccumulator 69 adds the offset address ADD_(OFF) with a sub-band addressADD output from the selector 70 by a number of times equal to the timesof counting by the down counter 65, and outputs the obtained addressdata to one input terminal of the accumulator 73.

The multiplier 72 calculates the product of the output value of theselector 71 and the value of the offset address ADD_(OFF), and outputsthe result to the other input terminal of the accumulator 73.

The selector 71 outputs the last truncation data set of the sub-bandspecified by the selection signal output from the sub-band selectioncircuit 64.

Because of the above configuration, the accumulator 73, insynchronization with the counting down timing of the down counter 65,generates an address for reading out data indicating an increase or adecrease in the amount of codes in each sub-band.

The code amount calculation circuit 80 includes a calculation unit 81, aregister 82, a register 83, an AND gate 84, and a comparator 85.

The addition-subtraction control signal generated in the addressgeneration circuit 60 is input to the addition-subtraction controlterminal of the calculation unit 81 of the code amount calculationcircuit 80. In addition, data indicating the amount of codes to betruncated, which is stored at the address specified by the addressgeneration circuit 60, is read out from either the memory C or thememory D which is in the enabled state, and is also input to theaddition-subtraction control terminal of the calculation unit 81 of thecode amount calculation circuit 80.

The calculation unit 81 inputs its last output to its own other inputterminal through the register 82. By such a configuration, the amount ofcodes to be truncated based on the truncation data set selectedpresently is loaded in the register 82.

The sub-band selection circuit 64 in the address generation circuit 60outputs the selection signal to one input terminal of the AND gate 84.The other input terminal of the AND gate 84 is connected to the register83.

The register 83 stores data having the same value as that of theselection signal output after the 1HH sub-band is selected, that is,after all sub-bands are selected, and before the first sub-band, thatis, the 3LL sub-band, is selected again.

Due to this, after all sub-bands are selected by the sub-band selectioncircuit 64, the AND gate 84 outputs a high level enabling signal to theenabling terminal of the comparator 85.

The comparator 85 compares the total amount of codes to be truncated ofall sub-bands output from the register 82 with a target value. If thetotal amount of codes to be truncated is higher than the target value,the comparator 85 outputs a high level signal to the data numberswitching circuit 90, and if the total amount of codes to be truncatedis lower than the target value, the comparator 85 outputs a low levelsignal to the data number switching circuit 90.

FIG. 11 is flowchart showing the operation of the data number switchingcircuit 90. Here, if the flowchart shown in FIG. 11 is input to thelogic synthesis tool made by the company Synopsys, USA, a specificcircuit can be automatically designed.

As shown in FIG. 11, in step S20, the data number switching circuit 90sets a processing index n equal to one.

In step S21, the data number switching circuit 90 sets the data number(T) of truncation data set equal to 128.

In step S22, the data number switching circuit 90 outputs the specifieddata number T to the DMA 33.

In step S23, the data number switching circuit 90 determines whether thecomparison result signal is input from the comparator 85 of the codeamount calculation circuit 80, which compares the total amount of codesto be truncated of all sub-bands with the target value.

If the comparison result signal is not input yet, the data numberswitching circuit 90 waits for the signal until it is input.

If the comparison result signal is input, the data number switchingcircuit 90 goes to the process in step S24.

In step S24, the data number switching circuit 90 identifies the presentvalue of the processing index n. According to the present value of theprocessing index n, and depending on whether the total amount of codesto be truncated is higher than the target value (high level comparisonresult signal), or the total amount of codes to be truncated is lowerthan the target value (low level comparison result signal), the datanumber switching circuit 90 conducts the following process.

Specifically, the data number switching circuit 90 goes to step S25 ifthe processing index n is one, to step S28 if the index n is two, tostep S31 if the index n is three, to step S34 if the index n is four, tostep S37 if the index n is five, to step S40 if the index n is six, tostep S43 if the index n is seven, and to step S48 if the index n isgreater than or equal to eight.

In step S25, the processing index n is one. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S26. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S27.

In step S26, the data number switching circuit 90 adds 128 to thepresent value of the data number T (128), and returns to step S22. Thatis, if the amount of codes to be truncated is lower than the targetvalue, the processing index n remains to be one.

In step S27, the data number switching circuit 90 subtracts 64 from thepresent value of the data number T (128), and goes to step S54, wherethe index n is increased by one. Then the data number switching circuit90 returns to step S22.

That is, if the amount of codes to be truncated is not lower than thetarget value, the processing index n is increased by one.

In step S28, the processing index n is two. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S29. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S30.

In step S29, the data number switching circuit 90 adds 32 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

In step S30, the data number switching circuit 90 subtracts 32 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

In step S31, the processing index n is three. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S32. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S33.

In step S32, the data number switching circuit 90 adds 16 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

In step S33, the data number switching circuit 90 subtracts 16 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

In step S34, the processing index n is four. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S35. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S36.

In step S35, the data number switching circuit 90 adds 8 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

In step S36, the data number switching circuit 90 subtracts 8 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

In step S37, the processing index n is five. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S38. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S39.

In step S38, the data number switching circuit 90 adds 4 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

In step S39, the data number switching circuit 90 subtracts 4 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

In step S40, the processing index n is six. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S41. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S42.

In step S41, the data number switching circuit 90 adds 2 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

In step S42, the data number switching circuit 90 subtracts 2 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

In step S43, the processing index n is seven. The data number switchingcircuit 90 determines whether the amount of codes to be truncated islower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S44. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S46.

In step S44, the data number switching circuit 90 adds 1 to the presentvalue of the data number T.

In step S45, the data number switching circuit 90 sets a flag F to zero,and goes to step S54, where the index n is increased by one. Then thedata number switching circuit 90 returns to step S22.

In step S46, the data number switching circuit 90 subtracts 1 from thepresent value of the data number T.

In step S47, the data number switching circuit 90 sets a flag F to one,and goes to step S54, where the index n is incremented by one. Then thedata number switching circuit 90 returns to step S22.

In step S48, the processing index n is greater than or equal to eight.The data number switching circuit 90 determines whether the flag F iszero.

If the flag F is zero, the data number switching circuit 90 goes to stepS49. If the flag F is not zero, the data number switching circuit 90goes to step S51.

In step S49, the data number switching circuit 90 determines whether theamount of codes to be truncated is lower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S50. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S53.

In step S50, the data number switching circuit 90 adds 1 to the presentvalue of the data number T, and goes to step S54, where the index n isincremented by one. Then the data number switching circuit 90 returns tostep S22.

Here, increasing the data number T by only one causes a change of thecomparison result of the amount of codes to be truncated with the targetvalue, that is, from the state in which the amount of codes to betruncated is lower than the target value to the state in which theamount of codes to be truncated is higher than the target value. Inother words, it can be concluded that the amount of codes to betruncated reaches to the target value.

In step S51, the data number switching circuit 90 determines whether theamount of codes to be truncated is lower than the target value.

If the amount of codes to be truncated is lower than the target value,the data number switching circuit 90 goes to step S53. If the amount ofcodes to be truncated is not lower than the target value, the datanumber switching circuit 90 goes to step S52.

In step S52, the data number switching circuit 90 subtracts 1 from thepresent value of the data number T, and goes to step S54, where theindex n is incremented by one. Then the data number switching circuit 90returns to step S22.

Here, the same as in step S50, decreasing the data number T by only onecauses a change of the comparison result of the amount of codes to betruncated with the target value, that is, from the state in which theamount of codes to be truncated is higher than the target value to thestate in which the amount of codes to be truncated is lower than thetarget value. In other words, it can be concluded that the amount ofcodes to be truncated reaches to target value.

In step S53, the data number switching circuit 90 determines thusobtained data number as the data number of truncation data set for use,and outputs a signal indicating the data number to the packetinformation generation circuit 34. Then the data number switchingcircuit 90 stops the processing.

The processing shown by the flowchart in FIG. 11 can be performed bysoftware executed in a not-illustrated central processing unit.

If the truncation table has such an arrangement of truncation data setsthat the amount of codes to be truncated decreases gradually when thedata number increases, leading to gradually improved quality of thereproduced image, in step S21, instead of setting the initial value ofthe data number to 128, the initial value of the data number may be setto the 128th data number from the last data number of the truncationtable. In addition, in the subsequent steps where the data number ismodified, the relevant operations are reversed, for example, theoperation of addition of 32 is changed to subtraction of 32.

Referring to FIG. 3 again, the packet information generation circuit 34calculates the number of coding passes in each sub-band determined bythe truncation data set corresponding to the data number selected by thedata number switching circuit 90, and the amount of codes of thesecoding passes. The packet information generation circuit 34 outputs theobtained result to the packet header generation circuit 36.

FIG. 12 is a flowchart showing the operation of the packet informationgeneration circuit 34. If the flowchart shown in FIG. 12 is input to thelogic synthesis tool made by the company Synopsys, USA, a specificcircuit can be automatically designed.

As shown in FIG. 12, in step S60, the packet information generationcircuit 34 determines whether a data number T of a truncation table isinput from the rate control circuit 32.

If the data number is not input yet, the packet information generationcircuit 34 waits for the data number until it is input.

If the data number is input, the packet information generation circuit34 goes to step S61.

In step S61, the packet information generation circuit 34 reads out thetruncation data set corresponding to the data number T from DRAM 50.

In step S62, from the obtained truncation data set, the packetinformation generation circuit 34 calculates the number of the residualcoding passes of each code block in each sub-band after code truncation.

In step S63, based on the obtained truncation data set, and from thedata loaded in the memory C and memory D, the packet informationgeneration circuit 34 calculates the amount of codes of the residualcoding passes of each code block in each sub-band after code truncation.

In step S64, the packet information generation circuit 34 outputs theobtained number of coding passes in each sub-band and the amount ofcodes to the packet header generation circuit 36.

The operations shown by the flowchart in FIG. 12 can be performed bysoftware executed in a not-illustrated central processing unit.

Referring to FIG. 3 again, the packet header generation circuit 36generates a packet header from the number of coding passes in eachsub-band and the amount of codes obtained by the packet informationgeneration circuit 34, the number of zero bit-planes, and codes read outby DMA 37 from DRAM 50. Then the packet header generation circuit 36outputs the generated packet header to the code formation circuit 38.

The code formation circuit 38 forms a bit stream using the data outputfrom the packet header generation circuit 36, and outputs the codes,which are truncated by an amount equaling to the target amount of codesto be truncated, to external devices.

Here, a well known circuit may be used as the packet header generationcircuit 36.

Second Embodiment

FIG. 13 is a block diagram showing a configuration of an imagecompression device 200 according to a second embodiment of the presentinvention.

The configuration of the image compression device 200 is basically thesame as that of the image compression device 100 in FIG. 3, except thatthe data processing circuit 210 of the arithmetic coding unit 20 and therate control circuit 220 of the packet header generation unit 30 in thepresent embodiment are different from the data processing circuit 29 ofthe arithmetic coding unit 20 and the rate control circuit 32 of thepacket header generation unit 30 in the preceding embodiment.

Below, only the data processing circuit 210 and the rate control circuit220 are described in detail, and the same reference numbers are used forthe same elements in the present embodiment as those in the precedingembodiment.

FIG. 14 is a flowchart showing the operation of the data processingcircuit 210. If the flowchart shown in FIG. 14 is input to the logicsynthesis tool made by the company Synopsys, USA, a specific circuit canbe automatically designed.

First, sub-bands are defined corresponding to values of the sub-banddetermining parameter SB. Specifically, SB=1 corresponds to a sub-band3LL, SB=2 corresponds to the sub-band 3HL, SB=3 corresponds to thesub-band 3LH, SB=4 corresponds to the sub-band 3HH, SB=5 corresponds tothe sub-band 2HL, SB=6 corresponds to the sub-band 2LH, SB=7 correspondsto the sub-band 2HH, SB=8 corresponds to the sub-band 1HL, SB=9corresponds to the sub-band 1LH, and SB=10 corresponds to the sub-band1HH.

As shown in FIG. 14, in step S70, the data processing circuit 210 setsthe parameter SB equal to one.

In step S71, the data processing circuit 210 sets a parameter BP equalto zero, and a variable D_(BP) equal to zero. The parameter BPdetermines the number of the coding passes, the codes in which are to betruncated. The variable D_(BP) represents the total amount of codes ofthe processed code blocks after codes of a number of BP coding passes inthe code blocks are truncated from the bit-plane of the leastsignificant bit.

In step S72, the data processing circuit 210 sets a parameter CB equalto one. Consecutive numbers 1, 2, 3, . . . are assigned to the codeblocks of the sub-band specified by the parameter SB, and the parameterCB determines one of the numbers.

In step S73, the data processing circuit 210 sets a parameter Q to avalue equaling the sum of the parameter BP and the number of masks M(CB)to be truncated in the code block specified by the parameter CB. Thatis, the parameter Q indicates the number of the coding passes to beactually truncated in the code block.

In step S74, the data processing circuit 210 performs a calculation toobtain the total amount of codes (represented by S_(BP)(CB))corresponding to the number of Q coding passes to be truncated from thebit-plane of the least significant bit of the code block specified bythe parameter CB.

The data processing circuit 210 determines the total amount of codes(represented by S_(ALL)(CB)) of the code block corresponding to thevalue of the parameter CB based on the output of the code amountcalculation circuit 28, and calculates a total amount of codes(represented by S_(BP)(CB)) corresponding to the number of Q codingpasses from data loaded in the memory A or the memory B. In addition,the data processing circuit 210 subtracts S_(BP)(CB) from S_(ALL)(CB)and obtains a variable D_(BP)(CB).

In step S75, the data processing circuit 210 assigns a sum of the valueof the variable D_(BP)(CB) and the value of the parameter D_(BP) to thevariable D_(BP)(CB); as mentioned above, the variable D_(BP) representsthe total amount of codes of the processed code blocks.

In step S76, the data processing circuit 210 increments the parameter CBby one.

In step S77, the data processing circuit 210 determines whether theparameter CB is greater than the maximum number CB_(SB-MAX) assigned tothe code blocks of the sub-band specified by the parameter SB.

If the parameter CB is not greater than the maximum number CB_(SB-MAX),the data processing circuit 210 goes back to step S73. If the parameterCB is greater than the maximum number CB_(SB-MA), the data processingcircuit 210 goes to step S78.

In step S78, the data processing circuit 210 stores the value of theparameter D_(BP) at an address equaling the sum of an offset addressADD_(OFF)×BP and an address ADD″SB″ in the memory selected from thememory A and the memory B, which are alternatively switched to theenabling state frame by frame.

For example, when the parameter SB is one, the address ADD″SB″represents the address ADD3LL.

In step S79, the data processing circuit 210 increases the parameter BPby one.

In step S80, the data processing circuit 210 determines whether theparameter BP is greater than 46. If the parameter BP is not greater than46, the data processing circuit 210 goes back to step S72.

If the parameter BP is greater than 46, that is, all of the 46 codingpasses of the sub-band specified by the parameter BP have beenprocessed, the data processing circuit 210 goes to step S81 to processthe next sub-band.

In step S81, in order to process the next sub-band, the data processingcircuit 210 increments the parameter SB by one.

In step S82, the data processing circuit 210 determines whether theparameter SB is greater than 10, which is the maximum of the parameterSB as defined above.

If the value of the parameter SB is not greater than 10, the dataprocessing circuit 210 returns to step S71.

If the value of the parameter SB is greater than 10, it means that allof the sub-bands have been processed, and the data processing circuit210 stops the routine.

The operations shown by the flowchart in FIG. 14 can be performed bysoftware executed in a not-illustrated central processing unit.

FIG. 15 is a diagram showing a memory map of the memory C of the imagecompression device 200. The memory D has the same memory map as thememory C.

As shown in FIG. 15, in the memory C, at an address ADD3LL, there areloaded data indicating the total amount of the residual codes. The totalamount of the residual codes is defined to be the amount of the codesafter truncating codes of the 46 coding passes of the sub-band 3LL codepass by code pass from the bit-plane of the least significant bit ineach sub-band, and after truncating codes of a number of M codingpasses, where M is the number of masks determined in each code block.

Similarly, at addresses ADD3HL, ADD3HL, ADD3HH, ADD2HL, ADD2LH, ADD2HH,ADD1HL, ADD1LH, and ADD1HH, there are respectively stored the dataindicating the total amount of the residual codes in the correspondingsub-bands.

Further, FIG. 15 shows data stored at address from ADD2HH to ADD1HL,specifically, the total amount of the residual codes are presented,which is the amount of the residual codes after truncating codes of the46 coding passes of the sub-band 3LL code pass by code pass from thebit-plane of the least significant bit in each sub-band, and aftertruncating codes of a number of coding passes equaling to the number ofmasks specified code block by code block.

Here, the total amount of the residual codes is denoted as Dn, where ntakes values from 0 to 46. The total amount of the residual codes isdefined to have a specified bit length, for example, 20 bits.

If the offset address ADD_(OFF) is determined, which is related to a20-bit long storage region, data indicating the amount of the residualcodes (Dn) when 0, or 1, or 2, . . . , or 46 code pass are truncated,can be loaded at an address equal to a sum of an address ADD2HH and theoffset address corresponding to the number of the truncated codingpasses, that is, the amounts of the residual codes (Dn) are respectivelyloaded at addresses ADD2HH, ADD2HH+ADD_(OFF), ADD2HH+2×ADD_(OFF),ADD2HH+3×ADD_(OFF), . . . , and ADD2HH+46×ADD_(OFF).

FIG. 16 is a block diagram showing a configuration of the rate controlcircuit 220 of the image compression device 200 according to the secondembodiment of the present invention.

As shown in FIG. 16, the rate control circuit 220 includes an addressgeneration circuit 230, a code amount calculation circuit 240, and adata number switching circuit 250.

The rate control circuit 220 reads out the truncation data setcorresponding to a data number 128 from the DRAM 50 through the DMA 31.According to the truncation data set read out from the DRAM 50, the ratecontrol circuit 220 reads out the data indicating the amount of codesafter truncating codes in each sub-band from the memory C or memory D,and calculates the sum of the amounts of codes. Then the rate controlcircuit 220 compares the calculated amount of codes with a target value.

If the calculated amount of codes is greater than the target value, therate control circuit 220 reads out the truncation data set correspondingto a data number greater than the previous one, and according to thetruncation data set, the rate control circuit 220 calculates again theamount of codes after code truncation.

On the other hand, if the calculated amount of codes is less than thetarget value, the rate control circuit 220 reads out the truncation dataset corresponding to a data number less than the previous one, andaccording to this truncation data set, the rate control circuit 220calculates again the amount of codes after code truncation.

In this way, the rate control circuit 220 determines the truncation dataset that results in a calculated amount of codes approximately equal tothe target value. The rate control circuit 220 outputs the determinedtruncation data set to the packet information generation circuit 34.

Based on the truncation data set input through the DMA 31, the addressgeneration circuit 230 generates an address signal for reading out theamount of codes after truncating codes in each sub-band, and outputs theaddress signal to the memory C or memory D.

The address generation circuit 230 outputs the data indicating theamount of codes after code truncation loaded at the specified address ineither the memory C or the memory D, which is in an enabled state andholds data of the image frame being processed, are output to the codeamount calculation circuit 240.

The address generation circuit 230 includes a register 231, a selector232, a sub-band selection circuit 233, a selector 234, a multiplier 235,and an accumulator 236.

The truncation data set that is output through the DMA 31 are input tothe register 231. The register 231 holds the truncation data set withthe truncation data set being divided into parts related to thesub-bands, respectively, (that is, the sub-bands 3LL, 3HL, 3LH, 3HH,2HL, 2LH, 2HH, 1HL, 1LH, and 1HH), and outputs the divided truncationdata set to the selector 232.

In response to a selection signal from the sub-band selection circuit233, the selector 232 sequentially outputs the truncation data sets ofall the sub-bands to one input terminal of the multiplier 235 in orderof sub-band 3LL, 3HL, 3LH, 3HH, 2HL, 2LH, 2HH, 1HL, 1LH, and 1HH. Thevalue of the offset address ADD_(OFF) is input to the other inputterminal of the multiplier 235.

The multiplier 235 outputs the offset address, which corresponds to thenumber of the coding passes to be truncated as specified by thetruncation data of the sub-band selected by the selection signal, to oneinput terminal of the accumulator 236.

The sub-band selection circuit 233 updates the selection signal so as toselect the next sub-band in synchronization with a clock signal CLK,which is input as a request signal for the selection signal.

The selection signal from the sub-band selection circuit 233 is alsoinput to the selector 234.

The selector 234 outputs a heading address ADD (ADD3LL through ADD1HH)of the sub-band determined by the selection signal to the other inputterminal of the accumulator 236.

Due to the above configuration, the accumulator 236 generates an addressfor storing the data indicting the amount of the residual codes which isobtained after truncating, from the bit-plane of the least significantbit, codes of coding passes specified by the truncation data set of thesub-band selected by the selection signal and codes of an additionalnumber of coding passes equaling to the number of masks. The accumulator236 then outputs the address data to the memory C or memory D.

The code amount calculation circuit 240 includes an accumulator 241, aregister 242, a register 243, an AND gate 244, and a comparator 255.

The code amount calculation circuit 240 calculates the total amount ofcodes after code truncation of all the sub-bands using the amounts ofcodes after code truncation in each sub-band sent from the memory C orthe memory D. The code amount calculation circuit 240 compares theobtained total amount of codes with a target value, generates a signalindicating the comparison result and outputs the signal to the datanumber switching circuit 250.

The data of the amount of codes read out by the code amount calculationcircuit 240 from the memory C or the memory D is input to one inputterminal of the accumulator 241. The data loaded in the register 242,which is the output of the accumulator 241, is input to the other inputterminal of the accumulator 241. By such a configuration, the sum of theamounts of codes in each sub-band, which are read out from the memory Cand the memory D, is loaded in the register 242 until a reset signal isinput to the register 242.

The sub-band selection circuit 233 in the address generation circuit 230outputs the selection signal to one input terminal of the AND gate 244.The other input terminal of the AND gate 84 is connected to the register243.

The register 243 loads data having the same value as that of theselection signal output after the 1HH sub-band is selected, that is,after all sub-bands are selected, and before the first sub-band, thatis, the 3LL sub-band, is selected again.

Due to this configuration, after selection signals of all the sub-bandsare output, and before the 3LL sub-band is selected again, the AND gate244 outputs a high level enabling signal to the enabling terminal of thecomparator 245 to switch the comparator 245 to an enabling state.

The comparator 245 compares the amount of codes after code truncationfrom the register 242 with a target value, generates a signal indicatingthe comparison result, and outputs the signal to the data numberswitching circuit 250.

The data number switching circuit 250 has the same configuration as thedata number switching circuit 90 of the image compression device in thefirst embodiment, and the detailed explanation is omitted.

Third Embodiment

FIG. 17 is a block diagram showing a configuration of an imagecompression device 300 according to a third embodiment of the presentinvention.

Similar to the image compression device 100 and the image compressiondevice 200 in the previous embodiments, the image compression device 300calculates the number of masks of each code block in each sub-band andamount of codes of each coding pass of each code block, and the amountof codes to be truncated for all the sub-bands when truncating codingpasses in each sub-band one by one based on a truncation data set. Bycomparing the obtained amount of codes to be truncated and a targetvalue, the image compression device 300 determines the most appropriatetruncation data set.

In the first embodiment, in order to calculate the amount of codes to betruncated for all the sub-bands, the image compression device 100calculates the change of the amount of codes, that is, the amount ofcodes to be truncated when truncating the codes of the coding passes ofcode blocks in each sub-band from the bit-plane of the least significantbit coding pass by coding pass, and loads the result of the change ofthe amount of codes in the memory C or the memory D in advance.

In contrast, in the present embodiment, in order to calculate the amountof codes to be truncated for all the sub-bands, when truncating codes ofthe coding passes of code blocks in each sub-band from the bit-plane ofthe least significant bit coding pass by coding pass, the imagecompression device 300 calculates the amount of codes to be truncatedwhen truncating codes of one coding pass, the amount of codes to betruncated when truncating codes of two coding passes, . . . , the amountof codes to be truncated when truncating codes of 46 coding passes,respectively, and loads these results in the memory C or the memory D inadvance. Here, the amount of codes to be truncated when truncating codesof one coding pass is actually the change of the amount of codes whentruncating codes of one coding pass, and the amount of codes to betruncated when truncating codes of two coding pass is defined to be thesum of the change of the amount of codes when truncating codes of thefirst coding pass and the change of the amount of codes when truncatingcodes of the second coding pass.

The configuration of the image compression device 200 is basically thesame as those of the image compression device 100 and the imagecompression device 200, except that the data processing circuit 310 ofthe arithmetic coding unit 20 and the rate control circuit 220 of thepacket header generation unit 330 in the present embodiment aredifferent from those in the previous embodiments.

Below, only the data processing circuit 310 and the rate control circuit320 are described in detail, and the same reference numbers are used forthe same elements in the present embodiment as those in the precedingembodiment.

FIG. 18 is a flowchart showing the operation of the data processingcircuit 310. Here, if the flowchart shown in FIG. 18 is input to thelogic synthesis tool made by the company Synopsys, USA, a specificcircuit can be automatically designed.

First, sub-bands are defined corresponding to values of the sub-banddetermining parameter SB. Specifically, SB=1 corresponds to the sub-band3LL, SB=2 corresponds to the sub-band 3HL, SB=3 corresponds to thesub-band 3LH, SB=4 corresponds to the sub-band 3HH, SB=5 corresponds tothe sub-band 2HL, SB=6 corresponds to the sub-band 2LH, SB=7 correspondsto the sub-band 2HH, SB=8 corresponds to the sub-band 1HL, SB=9corresponds to the sub-band 1LH, and SB=10 corresponds to the sub-band1HH.

As shown in FIG. 18, in step S90, the data processing circuit 310 setsthe parameter SB equal to one.

In step S91, the data processing circuit 310 sets a parameter BP equalto zero, and a variable S_(BP) equal to zero. The parameter BPdetermines the number of the coding passes, codes in which are to betruncated.

The variable S_(BP) indicates the total amount of the truncated codeswhen codes of a number of BP coding passes of the target code block aretruncated coding pass by coding pass from the bit-plane of the leastsignificant bit.

In step S92, the data processing circuit 310 sets a parameter CB equalto one. The parameter CB determines one of code blocks of the sub-bandspecified by the parameter SB, to which consecutive numbers 1, 2, 3, . .. are assigned.

In step S93, the data processing circuit 310 sets a parameter Q to avalue equaling the sum of the parameter BP and the number of masks M(CB)to be truncated in the code block specified by the parameter CB. Theparameter Q indicates the number of the coding passes, codes in whichare to be truncated in the code block.

In step S94, from data stored in the memory A or the memory B, the dataprocessing circuit 310 calculates the total amount of codes (representedby S_(BP)(CB)) of a number of Q coding passes from the bit-plane of theleast significant bit of the code block specified by the parameter CB.

In step S95, the data processing circuit 310 assigns the sum of thevalue of the variable S_(BP)(CB) and the value of the parameter S_(BP)to the parameter S_(BP).

In step S96, the data processing circuit 310 increments the parameter CBby one.

In step S97, the data processing circuit 310 determines whether theparameter CB is greater than the maximum number CB_(SB-MAX) assigned tothe code blocks of the sub-band specified by the parameter SB.

If the parameter CB is not greater than the maximum number CB_(SB-MAX),the data processing circuit 310 goes back to step S93. If the parameterCB is greater than the maximum number CB_(SB-MAX), the data processingcircuit 310 goes to step S98.

In step S98, the data processing circuit 310 stores the value of theparameter S_(BP) to an address equaling the sum of an offset addressADD_(OFF)×BP and an address ADD″SB″ in the memory selected from thememory A and the memory B, which are alternatively switched to theenabled state frame by frame.

For example, when the parameter SB is one, the address ADD″SB″represents the address ADD3LL.

In step S99, the data processing circuit 310 increments the parameter BPby one.

In step S100, the data processing circuit 310 determines whether theparameter BP is greater than 46. If the parameter BP is not greater than46, the data processing circuit 310 goes back to step S92.

If the parameter BP is greater than 46, that is, all of the 46 codingpasses of the sub-band specified by the parameter BP have beenprocessed, the data processing circuit 310 goes to step S101 to processthe next sub-band.

In step S101, in order to process the next sub-band, the data processingcircuit 310 increments the parameter SB by one.

In step S102, the data processing circuit 310 determines whether theparameter SB is greater than 10, which is the maximum of the parameterSB as defined above.

If the value of the parameter SB is not greater than 10, the dataprocessing circuit 310 returns to step S91.

If the value of the parameter SB is greater than 10, it means that allof the sub-bands have been processed, and the data processing circuit310 stops the routine.

The operations shown by the flowchart in FIG. 18 can be performed bysoftware executed in a not-illustrated central processing unit.

FIG. 19 is a block diagram showing a configuration of the rate controlcircuit 320 of the image compression device 300 according to the thirdembodiment of the present invention.

As shown in FIG. 19, the rate control circuit 320 includes an addressgeneration circuit 230, a code amount calculation circuit 340, and adata number switching circuit 250.

In the rate control circuit 320, only the code amount calculationcircuit 340 is different from the code amount calculation circuit 240 inthe previous embodiments.

In the second embodiment, a target amount of codes is input to thecomparator 245, but in the present embodiment, a target amount oftruncated data is input to the comparator 345. This is because the dataloaded in the memory C or the memory D are the amounts of truncatedcodes when truncating codes of one coding pass, two coding passes, . . ., and 46 coding passes, respectively, and the register 242 loads the sumof amounts of the truncated codes in each sub-band.

While the present invention is above described with reference tospecific embodiments chosen for purpose of illustration, it should beapparent that the invention is not limited to these embodiments, butnumerous modifications could be made thereto by those skilled in the artwithout departing from the basic concept and scope of the invention.

Summarizing the effect of the invention, according to the presentinvention, each of the first units is further divided into a number ofsecond units, and according to values of the coefficients of each of thesecond units, data truncation is performed second unit by second unit.Due to this, in comparison with the case in which codes are truncated ina single and large unit, that is, the first unit, it is possible toimprove the compression rate while maintaining quality of the reproducedimage.

By preparing truncation data sets arranged so that along with anincrease of the data numbers of the truncation data sets, the amount ofthe codes to be truncated increases or decreases gradually, and theimage quality degrades or improves gradually, it is not necessary toperform the process of decoding the codes after truncation according tothe JPEG 2000 algorithm and determine distortion relative to the imageprior to the code truncation, to determine the way of code truncationresulting in the least distortion.

This patent application is based on Japanese Priority Patent ApplicationNo. 2003-091307 filed on Mar. 28, 2003, the entire contents of which arehereby incorporated by reference.

1. An image compression device, comprising: an encoding part thatperforms a frequency analysis of image data, encodes a plurality ofcoefficients generated by the frequency analysis first unit by firstunit, and generates a plurality of codes; a code reduction part thatreduces the amount of the codes of each of the first units; and aprocessing part that further divides the coefficients or the codes ineach of the first units into a plurality of second units, and increasesthe amount of code reduction in the code reduction part for each of thesecond units according to values of the coefficients of each of thesecond units or according to values of the codes of each of the secondunits.
 2. The image compression device as claimed in claim 1, wherein:the code reduction part comprises: a truncation table including aplurality of truncation data sets to each of which a data number isassigned, said truncation data sets determining the amount of the codesto be truncated from the codes corresponding to one of the coefficientsfrom the least significant bit of the codes in each of the first units,said truncation data sets being arranged so that along with an increaseof the data number, the amount of the codes to be truncated increases ordecreases gradually, and the image quality degrades or improvesgradually; and a rate controller that determines one of the data numberscorresponding to one of the truncation data sets, said one of thetruncation data sets resulting in a change of the amount of the codes ofeach of the first units after code truncation in accordance with the oneof the truncation data sets to be close to a target value.
 3. The imagecompression device as claimed in claim 1, performing coding incompliance with the JPEG 2000 standards, wherein: the encoding partperforms a two-dimensional discrete wavelet transformation on the imagedata and generates a plurality of wavelet coefficients, divides thewavelet coefficients into a plurality of sub-bands, performs arithmeticcoding for the wavelet coefficients of each of the sub-bands andgenerates a plurality of codes; the code reduction part reduces theamount of the codes by truncating a portion of the codes correspondingto one of the wavelet coefficients from the least significant bit of thecodes in each of the sub-bands; and the processing part divides each ofthe sub-bands into a plurality of code blocks, and increases the amountof codes to be truncated in the code reduction part for each of the codeblocks according to values of the wavelet coefficients in each of thecode blocks or according to values of data obtained by processing thewavelet coefficients of each of the code blocks.
 4. The imagecompression device as claimed in claim 3, wherein: the processing partcomprises: an average value calculation circuit that calculates anaverage value of the wavelet coefficients of a plurality of effectivepixels in each of the code blocks, or an average value of the dataobtained by processing the wavelet coefficients of the effective pixelsin each of the code blocks; and a masking coefficient calculationcircuit that determines the increase of the amount of the codes to betruncated in each of the code blocks performed in the code reductionpart according to the average value obtained in the average valuecalculation circuit.
 5. The image compression device as claimed in claim4, wherein: the average value calculation circuit quantizes the waveletcoefficients of the effective pixels in each of the code blocks, andcalculates the average value of the data obtained by quantizing thewavelet coefficients.
 6. The image compression device as claimed inclaim 4, wherein: the average value calculation circuit encodes thewavelet coefficients of the effective pixels in each of the code blocksby the arithmetic coding, and calculates the average value of the dataobtained by encoding the wavelet coefficients.
 7. An image compressionmethod, comprising: a first step of performing a frequency analysis onimage data, encoding a plurality of coefficients obtained by thefrequency analysis first unit by first unit, and generating a pluralityof codes; a second step of reducing the amount of the codes of each ofthe first units; and a third step of further dividing the coefficientsor the codes of each of the first units into a plurality of secondunits, and increasing the amount of code reduction for each of thesecond units according to values of the coefficients of each of thesecond units or according to values of the codes of each of the secondunits.
 8. The image compression method as claimed in claim 7, wherein:the second step comprises: a step of creating a truncation tableincluding a plurality of truncation data sets to each of which a datanumber is assigned; said truncation data sets determining the amount ofthe codes to be truncated from the codes corresponding to one of thecoefficients from the least significant bit of the codes in each of thefirst units, said truncation data sets being arranged so that along withan increase of the data number, the amount of the codes to be truncatedincreases or decreases gradually, and the image quality degrades orimproves gradually; and a step of determining one of the data numberscorresponding to one of the truncation data sets, said one of thetruncation data sets resulting in a change of the amount of the codes ofeach of the first units after code truncation in accordance with the oneof the truncation data sets to be close to a target value.
 9. The imagecompression method as claimed in claim 7, performing coding incompliance with the JPEG 2000 standards, wherein: the first stepcomprises a step of performing a two-dimensional discrete wavelettransformation on the image data and generating a plurality of waveletcoefficients, dividing the wavelet coefficients into a plurality ofsub-bands, performing arithmetic coding for the wavelet coefficients ofeach of the sub-bands and generating a plurality of codes; the secondstep comprises a step of reducing the amount of the codes by truncatinga portion of the codes corresponding to one of the wavelet coefficientsfrom the least significant bit of the codes in each of the sub-bands;and the third step comprises a step of dividing each of the sub-bandsinto a plurality of code blocks, and increasing the amount of codes tobe truncated in the code reduction part for each of the code blocksaccording to values of the wavelet coefficients in each of the codeblocks or according to values of data obtained by processing the waveletcoefficients of each of the code blocks.
 10. The image compressionmethod as claimed in claim 9, wherein: the third step comprises: afourth step of calculating an average value of the wavelet coefficientsof a plurality of effective pixels in each of the code blocks, or anaverage value of the data obtained by processing the waveletcoefficients of the effective pixels in each of the code blocks; and afifth step of determining the increase of the amount of the codes to betruncated in each of the code blocks performed in the code reductionpart according to the average value obtained in the average valuecalculation circuit.
 11. The image compression method as claimed inclaim 10, wherein: the fourth step comprises a step of quantizing thewavelet coefficients of the effective pixels in each of the code blocks,and calculating the average value of the data obtained by quantizing thewavelet coefficients.
 12. The image compression method as claimed inclaim 10, wherein: the fourth step comprises a step of encoding thewavelet coefficients of the effective pixels in each of the code blocksby the arithmetic coding, and calculating the average value of the dataobtained by encoding the wavelet coefficients.
 13. A program forcompressing image data, comprising instructions for causing a computerto execute: a first step of performing a frequency analysis on the imagedata, encoding a plurality of coefficients obtained by the frequencyanalysis first unit by first unit, and generating a plurality of codes;a second step of reducing the amount of the codes of each of the firstunits; and a third step of further dividing the coefficients or thecodes of each of the first units into a plurality of second units, andincreasing the amount of code reduction for each of the second unitsaccording to values of the coefficients of each of the second units oraccording to values of the codes of each of the second units.
 14. Theprogram as claimed in claim 13, wherein: the second step comprises: astep of creating a truncation table including a plurality of truncationdata sets to each of which a data number is assigned, said truncationdata sets determining the amount of the codes to be truncated from thecodes corresponding to one of the coefficients from the leastsignificant bit of the codes in each of the first units, said truncationdata sets being arranged so that along with an increase of the datanumber, the amount of the codes to be truncated increases or decreasesgradually, and the image quality degrades or improves gradually; and astep of determining one of the data numbers corresponding to one of thetruncation data sets, said one of the truncation data sets resulting ina change of the amount of the codes of each of the first units aftercode truncation in accordance with the one of the truncation data setsto be close to a target value.
 15. The program as claimed in claim 13,said program performing image compression in compliance with the JPEG2000 standards, wherein: the first step comprises a step of performing atwo-dimensional discrete wavelet transformation on the image data andgenerating a plurality of wavelet coefficients, dividing the waveletcoefficients into a plurality of sub-bands, performing arithmetic codingfor the wavelet coefficients of each of the sub-bands and generating aplurality of codes; the second step comprises a step of reducing theamount of the codes by truncating a portion of the codes correspondingto one of the wavelet coefficients from the least significant bit of thecodes in each of the sub-bands; and the third step comprises a step ofdividing each of the sub-bands into a plurality of code blocks, andincreasing the amount of codes to be truncated in the code reductionpart for each of the code blocks according to values of the waveletcoefficients in each of the code blocks or according to values of dataobtained by processing the wavelet coefficients of each of the codeblocks.
 16. The program as claimed in claim 15, wherein: the third stepcomprises: a fourth step of calculating an average value of the waveletcoefficients of a plurality of effective pixels in each of the codeblocks, or an average value of the data obtained by processing thewavelet coefficients of the effective pixels in each of the code blocks;and a fifth step of determining the increase of the amount of the codesto be truncated in each of the code blocks performed in the codereduction part according to the average value obtained in the averagevalue calculation circuit.
 17. The program as claimed in claim 16,wherein: the fourth step comprises a step of quantizing the waveletcoefficients of the effective pixels in each of the code blocks, andcalculating the average value of the data obtained by quantizing thewavelet coefficients.
 18. The program as claimed in claim 16, wherein:the fourth step further comprises a step of encoding the waveletcoefficients of the effective pixels in each of the code blocks by thearithmetic coding, and calculating the average value of the dataobtained by encoding the wavelet coefficients.
 19. A storage medium thatstores a program for compressing image data and comprising instructionsfor causing a computer to execute: a first step of performing afrequency analysis on the image data, encoding a plurality ofcoefficients obtained by the frequency analysis first unit by firstunit, and generating a plurality of codes; a second step of reducing theamount of the codes of each of the first units; and a third step offurther dividing the coefficients or the codes of each of the firstunits into a plurality of second units, and increasing the amount ofcode reduction for each of the second units according to values of thecoefficients of each of the second units or according to values of thecodes of each of the second units.
 20. The storage medium as claimed inclaim 19, wherein: in said program, the second step comprises: a step ofcreating a truncation table including a plurality of truncation datasets to each of which a data number is assigned, said truncation datasets determining the amount of the codes to be truncated from the codescorresponding to one of the coefficients from the least significant bitof the codes in each of the first units, said truncation data sets beingarranged so that along with an increase of the data number, the amountof the codes to be truncated increases or decreases gradually, and theimage quality degrades or improves gradually; and a step of determiningone of the data numbers corresponding to one of the truncation datasets, said one of the truncation data sets resulting in a change of theamount of the codes of each of the first units after code truncation inaccordance with the one of the truncation data sets to be close to atarget value.
 21. The storage medium as claimed in claim 19, wherein:the image compression is performed in compliance with the JPEG 2000standards, wherein: the first step comprises a step of performing atwo-dimensional discrete wavelet transformation on the image data andgenerating a plurality of wavelet coefficients, dividing the waveletcoefficients into a plurality of sub-bands, performing arithmetic codingfor the wavelet coefficients of each of the sub-bands and generating aplurality of codes; the second step comprises a step of reducing theamount of the codes by truncating a portion of the codes correspondingto one of the wavelet coefficients from the least significant bit of thecodes in each of the sub-bands; and the third step comprises a step ofdividing each of the sub-bands into a plurality of code blocks, andincreasing the amount of codes to be truncated in the code reductionpart for each of the code blocks according to values of the waveletcoefficients in each of the code blocks or according to values of dataobtained by processing the wavelet coefficients of each of the codeblocks.
 22. The storage medium as claimed in claim 21, wherein: in saidprogram: the third step comprises: a fourth step of calculating anaverage value of the wavelet coefficients of a plurality of effectivepixels in each of the code blocks, or an average value of the dataobtained by processing the wavelet coefficients of the effective pixelsin each of the code blocks; and a fifth step of determining the increaseof the amount of the codes to be truncated in each of the code blocksperformed in the code reduction part according to the average valueobtained in the average value calculation circuit.
 23. The storagemedium as claimed in claim 22, wherein: in said program: the fourth stepcomprises a step of quantizing the wavelet coefficients of the effectivepixels in each of the code blocks, and calculating the average value ofthe data obtained by quantizing the wavelet coefficients.
 24. Thestorage medium as claimed in claim 16, wherein: in said program: thefourth step further comprises a step of encoding the waveletcoefficients of the effective pixels in each of the code blocks by thearithmetic coding, and calculating the average value of the dataobtained by encoding the wavelet coefficients.